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final publication# 17113 rev: e amendment/ 0 issue date: november 1996 am29f040 4 megabit (524,288 x 8-bit) cmos 5.0 volt-only, sector erase flash memory distinctive characteristics n 5.0 v 10% for read and write operations minimizes system level power requirements n compatible with jedec-standards pinout and software compatible with single- power-supply flash superior inadvertent write protection n package options 32-pin plcc 32-pin tsop 32-pin pdip n minimum 100,000 write/erase cycles guaranteed n high performance 55 ns maximum access time n sector erase architecture uniform sectors of 64 kbytes each any combination of sectors can be erased. also supports full chip erase. n sector protection hardware method that disables any combination of sectors from write or erase operations n embedded erase algorithms automatically preprograms and erases the chip or any combination of sectors n embedded program algorithms automatically programs and veri?s data at speci?d address n data polling and toggle bit feature for detection of program or erase cycle completion n erase suspend/resume supports reading data from a sector not being erased n low power consumption 20 ma typical active read current 30 ma typical program/erase current n enhanced power management for standby mode <1 m a typical standby current standard access time from standby mode general description the am29f040 is a 4 mbit, 5.0 volt-only flash memory organized as 512 kbytes of 8 bits each. the am29f040 is offered in a 32-pin package. this device is designed to be programmed in-system with the standard system 5.0 v v cc supply. a 12.0 v v pp is not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the standard am29f040 offers access times between 55 ns and 150 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ) and output enable (oe ) controls. the am29f040 is entirely command set compatible with the jedec single-power-supply flash standard. commands are written to the command register using standard microprocessor write timings. register con- tents serve as input to an internal state machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 12.0 volt flash or eprom devices. the am29f040 is programmed by executing the pro- gram command sequence. this will invoke the embed- ded program algorithm which is an internal algorithm that automatically times the program pulse widths and veri?s proper cell margin. typically, each sector can be programmed and veri?d in less than one second. erase is accomplished by executing the erase com- mand sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automati- cally preprograms the array if it is not already pro- grammed before executing the erase operation. during erase, the device automatically times the erase pulse widths and veri?s proper cell margin.
2 am29f040 any individual sector is typically erased and veri?d in 1.0 seconds (if already completely preprogrammed). this device also features a sector erase architecture. the sector mode allows for 64k byte blocks of memory to be erased and reprogrammed without affecting other blocks. the am29f040 is erased when shipped from the factory. the device features single 5.0 v power supply opera- tion for both read and write functions. internally gener- ated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq7 or by the toggle bit feature on dq6. once the end of a program or erase cycle has been completed, the device internally resets to the read mode. amds flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability and cost effectiveness. the am29f040 memory electrically erases the entire chip or all bits within a sector simultaneously via fowler- nordheim tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection. flexible sector-erase architecture n eight 64 kbyte sectors n individual-sector, multiple-sector, or bulk-erase capability n individual or multiple-sector protection is user de?able 7ffffh 6ffffh 5ffffh 64 kbytes per sector 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh 00000h 17113e-1
am29f040 3 product selector guide block diagram family part no: am29f040 ordering part no: v cc = 5.0 v 5% -55 v cc = 5.0 v 10% -70 -90 -120 -150 max access time (ns) 55 70 90 120 150 ce (e ) access (ns) 55 70 90 120 150 oe (g ) access (ns) 25 30 35 50 55 erase voltage generator y-gating cell matrix x-decoder y-decoder address latch chip enable output enable logic pgm voltage generator timer v cc detector state control command register we ce oe a0?18 stb stb dq0?q7 v cc v ss 17113e-2 data latch input/output buffers
4 am29f040 connection diagrams pdip plcc tsop 17113e-3 v cc we a17 a14 a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 5 6 7 8 9 10 11 12 13 17 18 19 20 16 15 14 29 28 27 26 25 24 23 22 21 13130 2 3 432 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss dq3 dq4 dq5 dq6 a14 a13 a8 a9 a11 oe a10 ce dq7 a12 a15 a16 a18 v cc we a17 17113e-4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 a17 we v cc a18 a16 a15 a12 a7 a6 a5 a4 oe a10 ce dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 a17 we v cc a18 a16 a15 a12 a7 a6 a5 a4 oe a10 ce dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 17113e-5 29f040 standard pinout 29f040 reverse pinout
am29f040 5 pin configuration a0?18 = address inputs dq0?q7 = data input/output ce = chip enable oe = output enable we = write enable v ss = device ground v cc = device power supply (5.0 v 10% or 5%) logic symbol 19 8 dq0?q7 a0?18 ce (e ) oe (g ) we (w ) 17113e-6
6 am29f040 ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: valid combinations valid combinations list con?urations planned to be sup- ported in volume for this device. consult the local amd sales of?e to con?m availability of speci? valid combinations and to check on newly released combinations. temperature range c = commercial (0 c to +70 c) i = industrial (?0 c to +85 c) e = extended (?5 c to +125 c) package type p = 32-pin plastic dip (pd 032) j = 32-pin rectangular plastic leaded chip carrier (pl 032) e = 32-pin thin small outline package (tsop) standard pinout (ts 032) f = 32-pin thin small outline package (tsop) reverse pinout (tsr032) device number/description am29f040 4 megabit (524,288 x 8-bit) cmos 5.0 volt-only, sector erase flash memory am29f040 -55 e c optional processing blank = standard processing b = burn-in b speed option see product selector guide and valid combinations valid combinations am29f040-55 jc, ji, je, ec, ei, ee, fc, fi, fe am29f040-70 am29f040-90 pc, pcb, pi, pib, pe, peb, jc, jcb, ji, jib, je, jeb, ec, ecb, ei, eib, ee, eeb, fc, fcb, fi, fib, p11 fe, feb am29f040-120 am29f040-150
am29f040 7 table 1. am29f040 user bus operations legend: l = logic 0, h = logic 1, x = don? care. see dc characteristics for voltage levels. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to tables 2 and 4. 2. refer to table 3 for valid pd (program data) during a write operation. 3. refer to the section on sector protection. 4. we can be v il if oe is v il , oe at v ih initiates the write operations. read mode the am29f040 has two control functions which must be satis?d in order to obtain data at the outputs. ce is the power control and should be used for device selec- tion. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output en- able access time is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable for at least t acc ? oe time). standby mode the am29f040 has two standby modes, a cmos standby mode (ce input held at v cc 0.5 v), when the current consumed is less than 5 m a; and a ttl standby mode (ce is held at v ih ) when the current required is reduced to approximately 1 ma. in the standby mode the outputs are in a high impedance state, independent of the oe input. if the device is deselected during erasure or program- ming, the device will draw active current until the operation is completed. output disable with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding pro- gramming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a9. two identi?r bytes may then be sequenced from the device outputs by toggling address a0 from v il to v ih . all addresses are don? cares except a0, a1, and a6. the manufacturer and device codes may also be read via the command register, for instances when the am29f040 is erased or programmed in a system with- out access to high voltage on the a9 pin. the command sequence is illustrated in table 4 (refer to autoselect command section). byte 0 (a0 = v il ) represents the manufacturers code (amd = 01h) and byte 1 (a0 = v ih ) the device identi?r code (am29f040 = a4h). all identi?rs for manufac- turer and device exhibit odd parity with the msb (dq7) de?ed as the parity bit. see table 2. operation ce oe we a0 a1 a6 a9 i/o autoselect manufacturer code (note 1) l l h l l l v id code autoselect device code (note 1) l l h h l l v id code read (note 4) l l h a0 a1 a6 a9 rd standby h xxxxxx high z output disable l h h xxxx high z write l h l a0 a1 a6 a9 pd (note 2) verify sector protect (note 3) l lhlhlv id code autoselect device unprotect code l l h h h l v id code
8 am29f040 table 2. am29f040 autoselect codes *outputs 01h at protected sector addresses table 3. sector addresses write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens ?st. standard microprocessor write timings are used. refer to ac write characteristics and the erase/ programming waveforms for speci? timing parameters. sector protection the am29f040 features hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 8). the sector protect feature is enabled using programming equipment at the users site. the device is shipped with all sectors unprotected. alternatively, amd may pro- gram and protect sectors in the factory prior to shipping the device (amds expressflash service). it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a16, a17, and a18) are used to select the desired sector. the device produces a logical ? at dq0 for a pro- tected sector and a logical ? for an unprotected sector. see table 2 for autoselect codes. sector unprotect the am29f040 also features a sector unprotect mode so that a protected sector may be unprotected to incorporate any changes in the code. the sector unpro- tect is enabled using programming equipment at the users site. command de?itions device operations are selected by writing speci? ad- dress and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to read mode. table 4 de?es the valid register command sequences. note that the erase suspend (b0) and erase resume (30) commands are valid only while the sector erase operation is in progress. either of the two reset commands will reset the device (when applicable). type a18 a17 a16 a6 a1 a0 code (hex) dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 manufacturer id xxxv il v il v il 01h00000001 am29f040 device id xxxv il v il v ih a4h10100100 sector protection sector addresses v il v ih v il 01h* 00000001 a18 a17 a16 address range sa0 0 0 0 00000h?ffffh sa1 0 0 1 10000h?ffffh sa2 0 1 0 20000h?ffffh sa3 0 1 1 30000h?ffffh sa4 1 0 0 40000h?ffffh sa5 1 0 1 50000h?ffffh sa6 1 1 0 60000h?ffffh sa7 1 1 1 70000h?ffffh
am29f040 9 table 4. am29f040 command de?itions notes: 1. address bits a15, a16, a17, and a18 = x = don? care for all address commands except for program address (pa), sector address (sa), read address (ra), and autoselect sector protect verify. 2. bus operations are de?ed in table 1. 3. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a18, a17, a16 will uniquely select any sector (see table 3). 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we . 5. read from non-erasing sectors is allowed in the erase suspend mode. read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command reg- ister. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/ reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value en- sures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the speci? timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the device resides in the target system. prom programmers typically access the signature codes by raising a9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains a command autoselect operation to supplement traditional prom programming method- ology. the operation is initiated by writing the auto- select command sequence into the command register. following the command write, a read cycle from ad- dress xx00h retrieves the manufacture code of 01h. a read cycle from address xx01h returns the device code a4h (see table 2). all manufacturer and device codes will exhibit odd parity with the msb (dq7) de?ed as the parity bit. scanning the sector addresses (a16, a17, a18) while (a6, a1, a0) = (0, 1, 0) will produce a logical ? at device output dq0 for a protected sector. to terminate the operation, it is necessary to write the read/reset command sequence into the register. byte programming the device is programmed on a byte-by-byte basis. programming is a four bus cycle operation. there are two ?nlock write cycles. these are followed by the program setup command and data write cycles. ad- dresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens ?st. the command sequence read/reset bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data read/reset 1 xxxxh f0h read/reset 4 5555h aah 2aaah 55h 5555h f0h ra rd autoselect 4 5555h aah 2aaah 55h 5555h 90h 00h 01h 01h a4h byte program 4 5555h aah 2aaah 55h 5555h a0h pa pd chip erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h sector erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 30h sector erase suspend erase can be suspended during sector erase with addr (don? care), data (b0h) sector erase resume erase can be resumed after suspend with addr (don? care), data (30h)
10 am29f040 rising edge of ce or we (whichever happens ?st) begins programming. upon executing the embedded program algorithm command sequence the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq7 is equivalent to data written to this bit (see write operation status section) at which time the device returns to the read mode and ad- dresses are no longer latched. therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. programming is allowed in any sequence and across sector boundaries. beware that a data ? cannot be programmed back to a ?? attempting to do so may cause the device to exceed programming time limits (dq5 = 1) or result in an apparent success, according to the data polling algorithm, but a read from reset/read mode will show that the data is still ?? only erase operations can convert ?? to ??. figure 1 illustrates the embedded programming algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two ?nlock write cycles. these are followed by writing the ?etup command. two more ?nlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device auto- matically will program and verify the entire memory for an all zero data pattern prior to electrical erase. the chip erase is performed sequentially one sector at a time. the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and termi- nates when the data on dq7 is ? (see write operation status section) at which time the device returns to read the mode. figure 2 illustrates the embedded erase algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two ?nlock write cycles. these are followed by writing the ?etup command. two more ?nlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (data) is latched on the rising edge of we . a time-out of 80 m s from the rising edge of the last sector erase command will initiate the sector erase command(s). multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 80 m s, otherwise that command will not be ac- cepted. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 80 m s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs within the 80 m s time-out window the timer is reset. (monitor dq3 to determine if the sector erase window is still open, see section dq3, sector erase timer.) any command other than sector erase or erase suspend during this period resets the device to read mode, ignoring the previous command string. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (1 to 8). sector erase does not require the user to program the device prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the 80 m s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq7 is ?" (see write operation status section) at which time the device returns to read mode. during the execution of the sector erase command, only the erase suspend and erase resume commands are allowed. all other commands will be ignored. data poll- ing must be performed at an address within any of the sectors being erased. figure 2 illustrates the embedded erase algorithm using typical command strings and bus operations.
am29f040 11 erase suspend the erase suspend command allows the user to inter- rupt a sector erase operation and then perform data reads from a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written dur- ing the chip erase operation or embedded program al- gorithm. writing the erase suspend command during the sector erase time-out results in immediate termina- tion of the time-out period and suspension of the erase operation. any other command written during the erase sus- pend mode will be ignored except the erase resume command. writing the erase resume command resumes the erase operation. the addresses are ?on?-cares when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a max- imum of 15 m s to suspend the erase operation. when the device has entered the erase-suspended mode, dq7 bit will be at logic ?? and dq6 will stop toggling. the user must use the address of the erasing sector for reading dq6 and dq7 to determine if the erase opera- tion has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. an- other erase suspend command can be written after the chip has resumed erasing. write operation status table 5. write operation status dq7 data polling the am29f040 device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read the device produces the compliment of the data last written to dq7. upon completion of the embedded program algorithm, reading the device produces the true data last written to dq7. during the embedded erase algo- rithm, reading the device produces a ? at the dq7 output. upon completion of the embedded erase algo- rithm, reading the device produces a ? at the dq7 output. the ?wchart for data polling (dq7) is shown in figure 3. for chip erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse se- quence. for sector erase, the data polling is valid after the last rising edge of the sector erase we pulse. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. once the em- bedded algorithm operation is close to being com- pleted, the am29f040 data pins (dq7) may change asynchronously while the output enable (oe ) is as- serted low. this means that the device is driving status information on dq7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq7 has a valid data, the data outputs on dq0?q6 may be still invalid. the valid data on dq0?q7 will be read on the successive read attempts. the data polling feature is active during the embedded programming algorithm, embedded erase algorithm, erase suspend, or sector erase time-out (see table 5). status dq7 dq6 dq5 dq3 in progress byte programming in embedded algorithm dq7 toggle 0 0 embedded erase algorithm 0 toggle 0 1 erase suspended mode erase suspended sector 1 no toggle 0 1 non-erase suspended sector data data data data exceeded time limits byte-programming in embedded algorithm dq7 toggle 1 0 embedded erase algorithm 0 toggle 1 1
12 am29f040 see figure 12 for the data polling timing speci?ations and diagrams. dq6 toggle bit the am29f040 also features the ?oggle bit as a method to indicate to the host system that the embed- ded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the device will result in dq6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase we pulse. the toggle bit is active during the sector time out. in programming, if the sector being written to is pro- tected, the toggle bit will toggle for about 2 m s and then stop toggling without the data having changed. in erase, the device will erase all the selected sectors ex- cept for the ones that are protected. if all selected sec- tors are protected, the chip will toggle the toggle bit for about 100 m s and then drop back into read mode, hav- ing changed none of the data. either ce or oe toggling will cause the dq6 to toggle. see figure 13 for the toggle bit timing speci?ations and diagrams. dq5 exceeded timing limits dq5 will indicate if the program or erase time has ex- ceeded the specied limits (internal pulse count). under these conditions dq5 will produce a ?? this is a failure condition which indicates that the program or erase cycle was not successfully completed. data poll- ing is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in table 1. if this failure condition occurs during sector erase oper- ation, it speci?s that a particular sector is bad and it may not be reused, however, other sectors are still functional and may be used for the program or erase operation. the device must be reset to use other sec- tors. write the reset command sequence to the device, and then execute program or erase command se- quence. this allows the system to continue to use the other active sectors in the device. if this failure condition occurs during the chip erase op- eration, it speci?s that the entire chip is bad or combi- nation of sectors are bad. if this failure condition occurs during the byte program- ming operation, it speci?s that the entire sector con- taining that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). the dq5 failure condition may also appear if a user tries to program a ? to a location previously pro- grammed to ?? in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads a valid data on dq7 bit and dq6 never stops toggling. once the device has ex- ceeded timing limits, the dq5 bit will indicate a ?? please note that this is not a device failure condition since the device was incorrectly used. dq3 sector erase timer after the completion of the initial sector erase com- mand sequence the sector erase time-out will begin. dq3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, dq3 may be used to determine if the sector erase timer window is still open. if dq3 is high (?? the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit. if dq3 is low (??, the device will accept ad- ditional sector erase commands. to insure the com- mand has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the command may not have been accepted. refer to table 5, write operation status. data protection the am29f040 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist dur- ing power transitions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architec- ture, alteration of the memory contents only occurs after successful completion of specic multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise.
am29f040 13 low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, the am29f040 locks out write cycles for v cc < v lko (see dc characteristics section for voltages). when v cc < v lko , the command register is disabled, all internal program/erase circuits are disabled, and the device resets to the read mode. the am29f040 ignores all writes until v cc > v lko . the user must ensure that the control pins are in the correct logic state when v cc > v lko to prevent unintentional writes. write pulse ?litch protection noise pulses of less than 5 ns (typical) on oe , ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up. sector protect sectors of the am29f040 may be hardware protected using programming equipment at the users factory. the protection circuitry will disable both program and erase functions for the protected sector(s). requests to pro- gram or erase a protected sector will be ignored by the device.
14 am29f040 embedded algorithms start programming completed last address ? write program command sequence (see below) data poll device increment address ye s no 5555h/aah 2aaah/55h 5555h/a0h program address/program data program command sequence (address/command): 17113e-7 figure 1. embedded programming algorithm
am29f040 15 embedded algorithms start erasure completed write erase command sequence (see below) data polling or toggle bit successfully completed 5555h/aah 2aaah/55h 5555h/80h chip erase command sequence (address/command): 5555h/aah 2aaah/55h 5555h/10h 5555h/aah 2aaah/55h 5555h/80h individual sector/multiple sector erase command sequence (address/command): 5555h/aah sector address/30h sector address/30h sector address/30h 2aaah/55h additional sector erase commands are optional 17113e-8 figure 2. embedded erase algorithm
16 am29f040 start fail no dq7 = data ? no pass ye s no ye s dq7 = data ? dq5 = 1 ? ye s read byte (dq0?q7) addr = va read byte (dq0?q7) addr = va va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = xxxxh during chip erase 17113e-9 note: dq7 is rechecked even if dq5 = ? because dq7 may change simultaneously with dq5. figure 3. data polling algorithm
am29f040 17 note: dq6 is rechecked even if dq5 = ? because dq6 may stop toggling at the same time as dq5 changing to ?? figure 5. toggle bit algorithm figure 6. maximum negative overshoot waveform figure 7. maximum positive overshoot waveform start fail yes dq6 = data ? ye s pass no no ye s dq6 = data ? dq5 = 1 ? no read byte (dq0?q7) addr = va read byte (dq0?q7) addr = va va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = xxxxh during chip erase 17113e-10 20 ns 20 ns +0.8 v ?.5 v 20 ns ?.0 v 17113e-11 20 ns v cc + 0.5 v 2.0 v 20 ns 20 ns v cc + 2.0 v 17113e-12
18 am29f040 absolute maximum ratings storage temperature ceramic packages . . . . . . . . . . . . . . ?5 c to +150 c plastic packages . . . . . . . . . . . . . . . ?5 c to +125 c ambient temperature with power applied. . . . . . . . . . . . . . ?5 c to +125 c voltage with respect to ground all pins except a9 (note 1). . . . . . . . . ?.0 v to +7.0 v v cc (note 1). . . . . . . . . . . . . . . . . . . . ?.0 v to +7.0 v a9 (note 2). . . . . . . . . . . . . . . . . . . . ?.0 v to +13.0 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?.5 v. during voltage transitions, inputs may undershoot v ss to ?.0 v for periods of up to 20 ns. maximum dc voltage on input and i/o pins is v cc + 0.5 v. during voltage transitions, input and i/o pins may overshoot to v cc + 2.0 v for periods up to 20ns. 2. minimum dc input voltage on a9 pin is ?.5 v. during voltage transitions, a9 may undershoot v ss to ?.0 v for periods of up to 20 ns. maximum dc input voltage on a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this speci?ation is not implied. exposure of the device to absolute maximum rating conditions for ex- tended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0 c to +70 c industrial (i) devices ambient temperature (t a ). . . . . . . . . .?0 c to +85 c extended (e) devices ambient temperature (t a ). . . . . . . . .?5 c to +125 c v cc supply voltages v cc for am29f040-55. . . . . . . . . . +4.75 v to +5.25 v v cc for am29f040 -70, -90, -120, -150 . . . . . . . . . . . . +4.50 v to +5.50 v operating ranges de?e those limits between which the functionality of the device is guaranteed.
am29f040 19 dc characteristics ttl/nmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is less than 2 ma/mhz, with oe at v ih . 2. i cc active while embedded algorithm (program or erase) is in progress. 3. not 100% tested. parameter symbol parameter description test description min max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 m a i lit a9 input load current v cc = v cc max, a9 = 12.5 v 50 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 m a i cc1 v cc active read current (note 1) ce = v il, oe = v ih 30 ma i cc2 v cc active program/erase current (notes 2, 3) ce = v il, oe = v ih 40 ma i cc3 v cc standby current v cc = v cc max, ce = v ih 1.0 ma v il input low level ?.5 0.8 v v ih input high level 2.0 v cc + 0.5 v v id voltage for autoselect and sector protect v cc = 5.25 v 10.5 12.5 v v ol output low voltage i ol = 12 ma, v cc = v cc min 0.45 v v oh output high level i oh = ?.5 ma, v cc = v cc min 2.4 v v lko low v cc lock-out voltage 3.2 4.2 v
20 am29f040 dc characteristics (continued) cmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is less than 2 ma/mhz, with oe at v ih . 2. i cc active while embedded algorithm (program or erase) is in progress. 3. not 100% tested. 4. i cc3 = 20 m a max at extended temperatures (> +85 c). parameter symbol parameter description test description min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 m a i lit a9 input load current v cc = v cc max, a9 = 12.5 v 50 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 m a i cc1 v cc active read current (note 1) ce = v il, oe = v ih 20 30 ma i cc2 v cc active program/erase current (notes 2, 3) ce = vil, oe = vih 30 40 ma i cc3 v cc standby current (note 4) v cc = v cc max, ce = v cc 0.5 v 1 5 m a v il input low level ?.5 0.8 v v ih input high level 0.7 x v cc v cc + 0.3 v v id voltage for autoselect and sector protect v cc = 5.25 v 10.5 12.5 v v ol output low voltage i ol = 12.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?.5 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = ?00 m a, v cc = v cc min v cc ?.4 v v lko low v cc lock-out voltage 3.2 4.2 v
am29f040 21 ac characteristics read only operations characteristics notes: 1. test conditions (for -55): output load: 1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level, input and output: 1.5 v and 1.5 v (for all others): output load: 1 ttl gate and 100 pf input rise and fall times: 20 ns input pulse levels: 0.45 v to 2.4 v timing measurement reference level, input and output: 0.8 v and 2.0 v 2. output driver disable time. 3. not 100% tested. parameter symbols description test setup speed options (note 1) unit jedec standard -55 -70 -90 -120 -150 t avav t rc read cycle time (note 3) min 55 70 90 120 150 ns t avqv t acc address to output delay ce = v il oe = v il max 55 70 90 120 150 ns t elqv t ce chip enable to output delay oe = v il max 55 70 90 120 150 ns t glqv t oe output enable to output delay max 30 30 35 50 55 ns t ehqz t df chip enable to output high z (notes 2, 3) max 18 20 20 30 35 ns t ghqz t df output enable to output high z (notes 2, 3) 18 20 20 30 35 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min00000ns 2.7 k w diodes = in3064 or equivalent c l 6.2 k w 5.0 v in3064 or equivalent device under test 17113e-13 notes: for ?5: c l = 30 pf including jig capacitance for all others: c l = 100 pf including jig capacitance figure 8. test conditions
22 am29f040 ac characteristics write/erase/program operations notes: 1. this does not include the preprogramming time. 2. not 100% tested. parameter symbols description speed options unit jedec standard -55 -70 -90 -120 -150 t avav t wc write cycle time (note 2) min 55 70 90 120 150 ns t avwl t as address setup time min 00000ns t wlax t ah address hold time min 40 45 45 50 50 ns t dvwh t ds data setup time min 25 30 45 50 50 ns t whdx t dh data hold time min 00000ns t oes output enable setup time min 00000ns t oeh output enable hold time read (note 2) min 00000ns toggle and data polling (note 2) min 10 10 10 10 10 ns t ghwl t ghwl read recover time before write min 00000ns t elwl t cs ce setup time min 00000ns t wheh t ch ce hold time min 00000ns t wlwh t wp write pulse width min 30 35 45 50 50 ns t whwl t wph write pulse width high min 20 20 20 20 20 ns t whwh1 t whwh1 byte programming operation typ 77777 m s t whwh2 t whwh2 sector erase operation (note 1) typ11111sec max88888sec t whwh3 t whwh3 chip erase operation (note 1) typ88888sec max 64 64 64 64 64 sec t vcs v cc setup time (note 2) min 50 50 50 50 50 m s
am29f040 23 key to switching waveforms switching waveforms must be steady may change from h to l may change from l to h does not apply don? care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ?ff state waveform inputs outputs ks000010-pal addresses ce oe we outputs addresses stable high z high z (t df ) (t oh ) output valid t acc t oe (t ce ) t rc 17113e-14 figure 9. ac waveforms for read operations
24 am29f040 switching waveforms notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. figure 10. program operation timings note: sa is the sector address for sector erase. addresses = don? care for chip erase. figure 11. ac waveforms chip/sector erase operations d out pd t ah data polling t df t oh t oe t ds t cs t wph t dh t wp t ghwl addresses ce oe we data 5.0 v dq7 5555h pa a0h pa 17113e-15 t wc t rc t as t whwh1 t ce t wp t cs t dh 5555h 2aaah sa ce oe we data v cc aah 55h addresses 2aaah t vcs t ds 5555h t wph t ghwl t ah aah 55h 80h 10h/30h 17113e-16 t as 5555h
am29f040 25 switching waveforms *dq7 = valid data (the device has completed the embedded operation.) figure 12. ac waveforms for data polling during embedded algorithm operations *dq6 stops toggling (the device has completed the embedded operation.) figure 13. ac waveforms for toggle bit during embedded algorithm operations dq0 ?dq6 valid data t oe dq7 = valid data high z ce oe we dq7 dq0 ?dq6 dq0 ?dq6 = invalid * 17113e-17 t oeh t ce t ch t df t oh t whwh 1 or 2 dq7 t oeh ce t oh we oe t oe dq6 = stop toggling dq0?q7 valid dq6 = toggle dq6 = toggle data (dq0?q7) * t oes 17113e-18
26 am29f040 ac characteristics write/erase/program operations alternate ce controlled writes notes: 1. this does not include the preprogramming time. 2. not 100% tested. parameter symbols description speed options unit jedec standard -55 -70 -90 -120 -150 t avav t wc write cycle time (note 2) min 55 70 90 120 150 ns t avel t as address setup time min 00000ns t elax t ah address hold time min 40 45 45 50 50 ns t dveh t ds data setup time min 25 30 45 50 50 ns t ehdx t dh data hold time min 00000ns t oes output enable setup time min 00000ns t oeh output enable hold time read (note 2) min 00000ns toggle and data polling (note 2) min 10 10 10 10 10 ns t ghel t ghel read recover time before write min 00000ns t wlel t ws we setup time min 00000ns t ehwh t wh we hold time min 00000ns t eleh t cp ce pulse width min 30 35 45 50 50 ns t ehel t cph ce pulse width high min 20 20 20 20 20 ns t whwh1 t whwh1 byte programming operation typ 77777 m s t whwh2 t whwh2 sector erase operation (note 1) typ11111sec max88888sec t whwh3 t whwh3 chip erase operation (note 1) typ88888sec max 64 64 64 64 64 sec t vcs v cc setup time (note 2) min 30 50 50 50 50 m s
am29f040 27 switching waveforms notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. figure 14. alternate ce controlled program operation timings d out pd t ah data polling t ds t ws t cph t dh t cp t ghel addresses we oe ce data 5.0 v dq7 5555h pa a0h pa 17113e-19 t wc t as t whwh1
28 am29f040 erase and programming performance notes: 1. 25 c, 5 v v cc , 100,000 cycles. 2. under worst case condition of 90 c, 4.5 v v cc , 100,000 cycles. 3. system-level overhead is de?ed as the time required to execute the four bus cycle command necessary to program each byte. in the preprogramming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 4. the embedded algorithms allow for 1.8 ms byte program time. dq5 = ?" only after a byte takes the theoretical maximum time to program. a minimal number of bytes may require signi?antly more programming pulses than the typical byte. the majority of the bytes will program within one or two pulses (7 to 14 m s). this is demonstrated by the typical and maximum programming times listed above. latchup characteristics includes all pins except v cc . test conditions: v cc = 5.0 v, one pin at a time. lcc pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. parameter typ max unit comments sector erase time 1.0 (note 1) 8 sec excludes 00h programming prior to erasure chip erase time 8 (note 1) 64 sec excludes 00h programming prior to erasure byte programming time 7 (note 1) 300 (note 2) m s excludes system-level overhead (note 3) chip programming time 3.6 (note 1) 10.8 (notes 2, 4) sec excludes system-level overhead (note 3) min max input voltage with respect to v ss on all i/o pins ?.0 v v cc + 1.0 v v cc current ?00 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf
am29f040 29 plcc pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. pdip pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 4 6 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v pp = 0 8 12 pf parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 4 6 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v pp = 0 8 12 pf
30 am29f040 physical dimensions pd 032 32-pin plastic dip (measured in inches) pl 032 32-pin plastic leaded chip carrier (measured in inches) pin 1 i.d. 1.640 1.680 .530 .580 .005 min .045 .065 .090 .110 .140 .225 .120 .160 .014 .022 seating plane .015 .060 16-038-sb_ag pd 032 dg75 2-28-95 ae 32 17 16 .630 .700 0? 10 .600 .625 .008 .015 .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530
am29f040 31 physical dimensions (continued) ts 032 32-pin standard thin small outline package (measured in millimeters) pin 1 i.d. 1 18.30 18.50 7.90 8.10 0.50 bs c 0.05 0.15 0.95 1.05 16-038-tsop-2 ts 032 da95 8-14-96 lv 19.80 20.20 1.20 max 0.50 0.70 0.10 0.21 0 5 0.08 0.20 0.17 0.27
32 am29f040 physical dimensions (continued) tsr032 32-pin reversed thin small outline package (measured in millimeters) 1 18.30 18.50 19.80 20.20 7.90 8.10 0.50 bsc 0.05 0.15 0.95 1.05 16-038-tsop-2 tsr032 da95 8-15-96 lv pin 1 i.d. 1.20 max 0.50 0.70 0.10 0.21 0 5 0.08 0.20 0.17 0.27
am29f040 33 data sheet revision summary for am29f040 distinctive characteristics changed low power consumption speci?ations to typ- ical values. added ?nhanced power management bullet. general description fifth paragraph, changed sector erase time to 1.0 sec. product selector guide removed the -75 (70 ns, 5%) speed option. ordering information added -55 speed option to the example part number. removed the -75 speed option from the valid combina- tions. added industrial and extended temperature ranges to -55 valid combinations. added extended tem- perature to -70 valid combinations. table 1?ser bus operations changed i/o write entry to ?d and i/o read entry to ?d? now matches table 4. corrected reference to ta- bles in note 2. standby mode changed maximum cmos standby mode current to 5 m a. autoselect deleted fourth paragraph. table 2?utoselect codes changed table title. table 3?ector addresses changed table title. sector protection reworded second paragraph, second sentence. sector unprotection deleted after second sentence. table 4?ommand de?itions added ? to ?st cycle of ?st read/reset command. changed fourth cycle in byte program row from ?ata to ?d? deleted note 1. rewrote notes 2 and 6. sector erase changed time-out to 80 m s. deleted note. in second paragraph, deleted third sentence from end. in fourth paragraph, changed third sentence from end. user note for chip erase and sector erase commands deleted section. erase suspend deleted last sentence of fourth paragraph. deleted ?th paragraph. table 5?rite operation status added overbars to dq7. dq7?ata polling fourth paragraph, added ?rase suspend. dq5?xceeded timing limits clari?d ?st sentence in ?th paragraph. absolute maximum ratings corrected v ss in second sentence to v. operating ranges? cc supply voltages added -55 and -70 speed options. deleted -75 speed option. dc characteristics ttl/nmos compatible: changed i cc1 , i cc2 , and v id speci?ations. cmos compatible: changed i cc1 , i cc2 , i cc3 and v id speci?ations, added typical values. added note 4. ac characteristics read only operations characteristics: removed -75 speed option. changed t glqv in -55 column to 30 ns. combined notes 1 and 2. figure 7?est conditions changed ?st c l in note to -55. ac characteristics write/erase/program operations (also same table for alternate ce controlled writes): removed -75 speed option. changed speci?ations on t whwh1 , t whwh2 , and t whwh3 . erase and programming performance changed maximum speci?ations. clari?d note 5. de- leted note 2. trademarks copyright ?1996 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identi?ation purposes only and may be trademarks of their respective companies.

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